Semiconductor device package and method of manufacturing the same

ABSTRACT

A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device. A coefficient of thermal expansion (CTE) of the first emitting device is greater than a CTE of the second emitting device.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 16/789,243 filed Feb. 12, 2020, the contents of which is incorporated herein by reference in its entirety.

BACKGROUND 1. Technical Field

The present disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly to a semiconductor device package including an antenna and a method of manufacturing the same.

2. Description of the Related Art

Wireless communication devices, such as cell phones, typically include antennas for transmitting and receiving radio frequency (RF) signals. Comparably, a wireless communication device includes an antenna and a communication module, each disposed on different parts of a circuit board. Under the comparable approach, the antenna and the communication module are separately manufactured and electrically connected together after being placed on the circuit board. Accordingly, separate manufacturing costs may be incurred for both components. Furthermore, it may be difficult to reduce a size of the wireless communication device to attain a suitably compact product design. To reduce the cost and package size, an Antenna-in-Package (AiP) approach is provided. In general, an organic substrate is commonly used in an AiP system. However, due to the process limitation of the organic substrate, it is difficult to achieve fine-pitch (less than 15/15 μm), and the thickness of the organic substrate is relatively thick, which will hinder the miniaturization of the AiP system.

SUMMARY

In accordance with some embodiments of the present disclosure, a semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device. A coefficient of thermal expansion (CTE) of the first emitting device is greater than a CTE of the second emitting device. In some embodiment, the CTE may be equivalent CTE.

In accordance with some embodiments of the present disclosure, a semiconductor device package includes a building-up circuit, a first emitting device and a second emitting device. The building-up circuit has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the building-up circuit. The first emitting device has a first surface facing the building-up circuit and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device. A thickness of the second emitting device is greater than a thickness of the first emitting device.

In accordance with some embodiments of the present disclosure, a method of manufacturing an optical module includes (a) providing a first emitting device having a first conductive pattern; (b) providing a plurality of second emitting devices, each having a second conductive pattern; and (c) attaching the second emitting devices on the first emitting device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 1B illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 2A illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 2B illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 3 illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 4 illustrates a cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure.

FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D and FIG. 5E illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

FIG. 1A illustrates a cross-sectional view of a semiconductor device package 1A in accordance with some embodiments of the present disclosure. The semiconductor device package 1A includes carriers 10 a, 10 b, circuit layers 11, 13, 14, interconnection structures 12 a, 12 b, an electronic component 15, electrical contacts 16 and package bodies 17, 18 and 19.

In some embodiments, the carrier 10 a may be or include a glass substrate. In some embodiments, the carrier 10 a may be or include an emitting device having one or more emitting components (e.g., an antenna, a light emitting device, a sensor or the like) disposed thereon. The carrier 10 a may include conductive pad(s), trace(s), and interconnection(s) (e.g. via(s)). In some embodiments, the carrier 10 a may include transparent material. In some embodiments, the carrier 10 a may include opaque material. The carrier 10 a includes a material having a dielectric constant (Dk) less than approximately 5. The carrier 10 a includes a material having a Dk less than approximately 3. The carrier 10 a includes a material having a loss tangent or dissipation factor (Df) less than approximately 0.005. The carrier 10 a includes a material having a loss tangent or Df less than approximately 0.003.

The carrier 10 a has a surface 101 a, a surface 102 a opposite to the surface 101 a and a lateral surface 103 a extending between the surface 101 a and the surface 102 a. Compared to the organic substrate, it is easier to control the thickness of a glass carrier, which can facilitate the miniaturization of the semiconductor device package 1A. In some embodiments, the thickness of the carrier 10 a is equal to or less than about 400 μm. For example, the thickness of the carrier 10 a is in a range from about 50 μm to about 400 μm. For example, the thickness of the carrier 10 a is in a range from about 100 μm to about 300 μm. In some embodiments, a coefficient of thermal expansion (CTE) of the carrier 10 a is in a range from about 0.5 to about 13. In some embodiments, the CTE of the carrier 10 a is in a range from about 3.6 to about 8.5.

A conductive layer 10 p is disposed on the surface 102 a of the carrier 10 a. In some embodiments, the conductive layer 10 p defines a patterned antenna, such as a directional antenna, an omnidirectional antenna, an antenna array. For example, the conductive layer 10 p defines a patch antenna. The conductive layer 10 p is, or includes, a conductive material such as a metal or metal alloy. Examples of the conductive material include gold (Au), silver (Ag), copper (Cu), platinum (Pt), Palladium (Pd), other metal(s) or alloy(s), or a combination of two or more thereof. In some embodiments, the conductive layer 10 p may be replaced by one or more light emitting devices or sensors.

The carrier 10 b is disposed on the surface 101 a of the carrier 10 a. The carrier 10 b has a surface 101 b facing away from the carrier 10 a, a surface 102 b opposite to the surface 101 b and a lateral surface 103 b extending between the surface 101 b and the surface 102 b. The surface 102 b of the carrier 10 b is connected to the surface 101 a of the carrier 10 a through an adhesive layer 10 h (e.g., a tape, a glue or a die attach film (DAF)). The carrier 10 b is spaced apart from the carrier 10 a. For example, there is a distance (e.g., a thickness of the adhesive layer 10 a) between the surface 101 a of the carrier 10 a and the surface 102 b of the carrier 10 b. In some embodiments, the lateral surface 103 a of the carrier 10 a and the lateral surface 103 b of the carrier 10 b are noncoplanar or discontinuous. For example, the lateral surface 103 a of the carrier 10 a is recessed from the lateral surface 103 b of the carrier 10 b. For example, a width of the carrier 10 a is less than a width of the carrier 10 b. In some embodiments, a roughness of the lateral surface 103 a of the carrier 10 a is less than a roughness of the lateral surface 103 b of the carrier 10 b. In some embodiments, the carrier 10 b and a portion of the circuit layer 11 (e.g., a conductive layer of the circuit layer adjacent to the carrier 10 b) may be also referred to as a first emitting device.

In some embodiments, the carrier 10 b and the carrier 10 a may include the same thickness. Alternatively, the carrier 10 b and the carrier 10 a may include different thicknesses. For example, the thickness of the carrier 10 a can be equal to, greater than or less than the thickness of the carrier 10 b. In some embodiments, a sum of the thickness of the carrier 10 a and the thickness of the carrier 10 b may be equal to or less than about 400 μm. For example, the thickness of the carrier 10 a may be about 350 μm and the thickness of the carrier 10 b may be about 50 For example, the thickness of the carrier 10 a may be about 300 μm and the thickness of the carrier 10 b may be about 100 For example, the thickness of the carrier 10 a may be about 250 μm and the thickness of the carrier 10 b may be about 150 μm.

In some embodiments, the carrier 10 b and the carrier 10 a may include the same material. Alternatively, the carrier 10 b and the carrier 10 a may include different materials. In some embodiments, the CTE of the carrier 10 b is higher than the CTE of the carrier 10 a. In some embodiments, the hardness of the carrier 10 b is higher than the hardness of the carrier 10 a. By disposing a carrier 10 b having a relatively higher CTE and hardness between the carrier 10 a and the circuit layer 11, the warpage issue caused due to the CTE mismatch between the carrier 10 b and the package body 17 (or the package body 18) can be mitigated. In some embodiments, the Dk of the carrier 10 a is lower than the Dk of the carrier 10 b. By choosing the carrier 10 a having the relatively lower Dk, the electrical performance of the antenna pattern (e.g., the conductive layer 10 p) can be improved. This would increase the flexibility to design the semiconductor device package 1A.

The package body 17 is disposed on the surface 102 b of the carrier 10 b. The package body 17 covers the carrier 10 a and the conductive layer 10 p. The package body 17 covers the surface 102 a and the lateral surface 103 a of the carrier 10 a and a lateral surface of the adhesive layer 10 h. In some embodiments, the package body 17 has a lateral surface 173 substantially coplanar with the lateral surface 103 b of the carrier 10 b. The lateral surface 103 a of the carrier 10 a is recessed from the lateral surface 173 of the package body 17. For example, there is a distance between the lateral surface 103 a of the carrier 10 a and the lateral surface 173 of the package body 17. In some embodiments, the package body 17 includes an epoxy resin including fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof.

The circuit layer 11 (or building-up circuit) has a surface 111 facing away from the carrier 10 b, a surface 112 opposite to the surface 111 and a lateral surface 113 extending between the surface 111 and the surface 112. The circuit layer 11 is disposed on the surface 101 b of the carrier 10 b. In some embodiments, the circuit layer 11 is in contact with the carrier 10 b. Alternatively, the circuit layer 11 can be connected to the carrier 10 b through an adhesive layer (e.g., DAF). In some embodiments, the lateral surface 113 of the circuit layer 11 is substantially coplanar with the lateral surface 103 b of the carrier 10 b.

The circuit layer 11 includes one or more conductive layers (e.g., redistribution layers, RDLs) 11 c and one or more dielectric layers 11 d. A portion of the conductive layer 11 c is covered or encapsulated by the dielectric layer 11 d while another portion of the conductive layer 11 c is exposed from the dielectric layer 11 d to provide electrical connections. In some embodiments, the exposed portion of the conductive layer 11 c has a surface facing the carrier 10 b and in contact with the surface 101 b of the carrier 10 b. In some embodiments, the conductive layer 11 c may be or include one or more antenna patterns, light emitting devices, sensors or the like.

In some embodiments, the dielectric layer 11 d may include pre-impregnated composite fibers (e.g., pre-preg), Borophosphosilicate Glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, Undoped Silicate Glass (USG), any combination of two or more thereof, or the like. Examples of a pre-preg may include, but are not limited to, a multi-layer structure formed by stacking or laminating a number of pre-impregnated materials/sheets. In some embodiments, there may be any number of conductive layers 11 c and dielectric layers 11 d depending on design specifications. In some embodiments, the conductive layer 11 c is formed of or includes Au, Ag, Cu, Pt, Pd, or an alloy thereof.

One or more interconnection structures 12 a (e.g., conductive pillars or conductive elements) are disposed on the surface 111 of the circuit layer 11. The interconnection structures 12 a are electrically connected to the circuit layer 11 (i.e., to the conductive layer 11 c exposed from the dielectric layer 11 d). In some embodiments, the interconnection structures 12 a define an antenna structure. The interconnection structure 12 a is, or includes, a conductive material such as a metal or metal alloy. Examples of the conductive material include Au, Ag, Cu, Pt, Pd, or an alloy thereof.

The package body 18 is disposed on the surface 111 of the circuit layer 11. The package body 18 covers the interconnection structures 12 a. In some embodiments, the package body 18 has a lateral surface 183 substantially coplanar with the lateral surface 113 of the circuit layer 11. In some embodiments, the package body 18 includes an epoxy resin including fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof.

The circuit layer 13 (or building-up circuit) is disposed on the package body 18. The circuit layer 13 has a dielectric layer 13 d and a conductive layer 13 c. In some embodiments, the dielectric layer 13 d may include the same material as the dielectric layer 11 d. Alternatively, the dielectric layer 13 d and the dielectric layer 11 d may include different materials. The circuit layer 13 is electrically connected to the interconnection structures 12 a. For example, the conductive layer 13 c of the circuit layer 13 is in contact with the interconnection structures 12 a. Alternatively, there is a seed layer disposed between the conductive layer 13 c and the interconnection structures 12 a. In some embodiments, there may be any number of conductive layers 13 c and dielectric layers 13 d depending on design specifications.

One or more interconnection structures 12 b (e.g., conductive pillars or conductive elements) are disposed on a surface of the circuit layer 13 facing away from the circuit layer 11. The interconnection structures 12 b are electrically connected to the circuit layer 13. The interconnection structure 12 b is, or includes, a conductive material such as a metal or metal alloy. Examples of the conductive material include Au, Ag, Cu, Pt, Pd, or an alloy thereof.

The package body 19 is disposed on the surface of the circuit layer 13 facing away from the circuit layer 11. The package body 19 covers the interconnection structures 12 b and the electronic component 15. In some embodiments, the package body 19 has a lateral surface substantially coplanar with the lateral surface of the circuit layer 13. In some embodiments, the package body 19 includes an epoxy resin including fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including a silicone dispersed therein, or a combination thereof.

The circuit layer 14 (or building-up circuit) is disposed on the package body 19. The circuit layer 14 has a dielectric layer 14 d and a conductive layer 14 c. In some embodiments, the dielectric layer 14 d may include the same material as the dielectric layer 11 d. Alternatively, the dielectric layer 14 d and the dielectric layer 11 d may include different materials. The conductive layer 14 c is electrically connected to the interconnection structures 12 b. For example, the conductive layer 14 c of the circuit layer 14 is in contact with the interconnection structures 12 b. Alternatively, there is a seed layer disposed between the conductive layer 14 c and the interconnection structures 12 b. In some embodiments, there may be any number of conductive layers 14 c and dielectric layers 14 d depending on design specifications.

The electronic component 15 is disposed on a surface of the circuit layer 13 facing away from the circuit layer 11. The active surface of the electronic component 15 faces the circuit layer 13. The electronic component 15 is electrically connected to the circuit layer 13 (e.g., to the conductive layer 13 c) through electrical contacts (e.g., solder balls), and the electrical connection can be achieved by, for example, flip-chip technique. The electronic component 15 may be an active electronic component, such as an integrated circuit (IC) chip or a die.

The electrical contacts 16 are disposed on the conductive layer 14 c exposed from the dielectric layer 14 d. In some embodiments, the electrical contacts 16 may include solder or other suitable material(s).

In some embodiments, the lateral surface 103 a of the carrier 10 a may be coplanar with the lateral surface 103 b of the carrier 10 b. For example, the lateral surface 103 a of the carrier 10 a is exposed from the package body 17. Such structure may be formed by: (i) providing a glass wafer; (ii) forming the circuit layers 11, 13, 14, the interconnection structures 12 a, 12 b and the package bodies 17, 18, 19 and the electronic component 15 on the glass wafer; and (iii) performing a singulation through the circuit layers 11, 13, 14, the package bodies 17, 18, 19 and the carrier wafer. To meeting the requirement of the performance of the antenna structure, the glass wafer should select a material having a relatively low Dk (e.g., less than 5). However, a glass wafer having a relatively low Dk would have a relatively low CTE as well (e.g., less than 13). Due to a CTE mismatch between the glass wafer and the package body 17 (e.g., the package body generally has a CTE greater than 20), the warpage issues would occur. As the size of the glass wafer increases, the warpage issue becomes severer, which may result in the crack or damage of the glass wafer.

In accordance with the embodiments as shown in FIG. 1A, the lateral surface 103 a of the carrier 10 a is recessed from the lateral surface 103 b of the carrier 10 b. Such structure may be formed by (detailed operations would be described later): (i) performing a singulation for a glass wafer to divide the glass wafer into a plurality glass carriers (e.g., the carrier 10 a as shown in FIG. 1A); (ii) forming the carrier 10 b, the circuit layers 11, 13, 14, the interconnection structures 12 a, 12 b and the package bodies 17, 18, 19 and the electronic component 15; and (iii) attaching the carrier 10 a on the carrier 10 b through the adhesive layer 10 h. Since the size of the divided glass carrier is much less than that of the glass wafer, the warpage issue can be significantly mitigated. In addition, since it is unnecessary to select a material of the carrier 10 a having a higher CTE to be close to the CTE of the package body 17, materials having lower CTE (also having lower Dk) can be selected as the carrier 10 a. This would enhance the performance of the antenna structure of the semiconductor device package 1A. Furthermore, the thickness of the carrier 10 a can be reduced as well, which would facilitate the miniaturization of the semiconductor device package 1A.

FIG. 1B illustrates a cross-sectional view of a semiconductor device package 1B in accordance with some embodiments of the present disclosure. The semiconductor device package 1B is similar to the semiconductor device package 1A as shown in FIG. 1A, and one of the differences therebetween is that in FIG. 1B, a width of the adhesive layer 10 h is greater than a width of the carrier 10 a. For example, a lateral surface of the adhesive layer 10 h is substantially coplanar with the lateral surface 103 b of the carrier 10 b. For example, the lateral surface 103 a of the carrier 10 a is recessed from the lateral surface of the adhesive layer 10 h. This would increase the accuracy of the alignment between the carrier 10 a and the carrier 10 b during the manufacturing process.

FIG. 2A illustrates a cross-sectional view of a semiconductor device package 2A in accordance with some embodiments of the present disclosure. The semiconductor device package 2A is similar to the semiconductor device package 1A as shown in FIG. 1A, and the differences therebetween are described below.

The electronic component 15 is disposed on a surface of the circuit layer 13 facing away from the circuit layer 11. The backside surface of the electronic component 15 is connected to the circuit layer 13 through an adhesive layer 15 a (e.g., DAF). The electronic component 15 is electrically connected to the circuit layer 14 (e.g., to the conductive layer 14 c) through the interconnection structures 15 c (e.g., Cu pillars).

FIG. 2B illustrates a cross-sectional view of a semiconductor device package 2B in accordance with some embodiments of the present disclosure. The semiconductor device package 2B is similar to the semiconductor device package 2A as shown in FIG. 2A, and one of the differences therebetween is that in FIG. 2B, a width of the adhesive layer 10 h is greater than a width of the carrier 10 a. For example, a lateral surface of the adhesive layer 10 h is substantially coplanar with the lateral surface 103 b of the carrier 10 b. For example, the lateral surface 103 a of the carrier 10 a is recessed from the lateral surface of the adhesive layer 10 h. This would increase the accuracy of the alignment between the carrier 10 a and the carrier 10 b during the manufacturing process.

FIG. 3 illustrates a cross-sectional view of a semiconductor device package 3 in accordance with some embodiments of the present disclosure. The semiconductor device package 3 is similar to the semiconductor device package 1B as shown in FIG. 1B, and the differences therebetween are described below.

The semiconductor device package 3 may include two parts 3A and 3B. The part 3A includes the dielectric layer 13 d 1, the package body 19, the electronic component 15, the circuit layer 14, the interconnection structures 12 b and the electrical contacts 16. The part 3B includes the dielectric layer 13 d 2, the package bodies 17, 18, the circuit layer 11, the carriers 10 a and 10 b. The part 3A and the part 3B may be manufactured individually and then connected to each other through electrical contacts 31 s (e.g., solder balls). This would increase the yield rate of the semiconductor device package 3. In some embodiments, an underfill 31 h may be disposed between the part 3A and the part 3B to cover the electrical contacts 31 s. In some embodiments, a width of the part 3A is the same as a width of the part 3B. Alternatively, the width of the part 3A may be greater than or less than the width of the part 3B depending on design specifications.

FIG. 4 illustrates a cross-sectional view of a semiconductor device package 4 in accordance with some embodiments of the present disclosure. The semiconductor device package 4 is similar to the semiconductor device package 3 as shown in FIG. 3, and the differences therebetween are described below.

The semiconductor device package 4 may include two parts 4A and 4B. The part 4B is similar to the part 3B of the semiconductor device package 3 in FIG. 3. The part 4A is similar to the part 3A of the semiconductor device package 3 in FIG. 3 except that in the part 4A of the semiconductor device package 4 in FIG. 4, the electronic component 15 is disposed on a surface of the circuit layer 14 facing the dielectric layer 13 d 2. The backside surface of the electronic component 15 is connected to the surface of the circuit layer 14 through the adhesive layer 15 a. The active surface of the electronic component 15 is electrically connected to the conductive layer 13 c through the interconnection structures 15 c (e.g., Cu pillars). In some embodiments, a width of the part 4A is the same as a width of the part 4B. Alternatively, the width of the part 4A may be greater than or less than the width of the part 4B depending on design specifications.

FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D and FIG. 5E illustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure. In some embodiments, the method in FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D and FIG. 5E can be used to manufacture the semiconductor device package 1A in FIG. 1A.

Referring to FIG. 5A, a carrier 10 b is provided. The substrate 10 b may be in a wafer type, a panel type or a strip type. A circuit layer 11 including one or more conductive layers 11 c and one or more dielectric layers 11 d is formed on the carrier 10 b. Interconnection structures 12 a are formed on the circuit layer 11 to be electrically connected to the circuit layer 11 (e.g., connected to a portion of the conductive layer 11 c exposed from the dielectric layer 11 d). The dielectric layer 11 d is formed by, for example but is not limited to, photolithographic technique. In some embodiments, the interconnection structures 12 a may be formed by, for example but is not limited to, plating technique.

A package body 18 is then formed on the circuit layer 11 to cover the interconnection structures 12 a. In some embodiments, the package body 18 may be formed to fully cover the interconnection structures 12 a. In some embodiments, the package body 18 is formed by, for example, by a transfer molding technique, a compression technique or any other suitable techniques.

Referring to FIG. 5B, a portion of the carrier 10 b is removed by, for example, grinding or any other suitable processes to reduce the thickness of the carrier 10 b. In some embodiments, the thinning operation is carried out from a surface of the carrier 10 b facing away the circuit layer 11. In some embodiments, after the thinning operation, the thickness of the carrier 10 b is equal to or less than 200 μm. For example, the thickness of the carrier 10 b is equal to or less than 100 μm. For example, the thickness of the carrier 10 b is equal to or less than 50 μm.

Referring to FIG. 5C, the package body 18 is disposed on a carrier 59. The package body 18 may be attached to the carrier 59 through an adhesive layer (e.g., a tape or a glue). A carrier 10 a having a conductive layer 10 p thereon is disposed on the carrier 10 b. In some embodiments, the carrier 10 a is attached to the carrier 10 b through an adhesive layer 10 h. In some embodiments, the carrier 10 a may be formed by performing a singulation to divide a glass wafer into a plurality of glass carriers including the carrier 10 a. In some embodiments, the thickness of the carrier 10 a is equal to or greater than 200 μm. For example, the thickness of the carrier 10 a is equal to or greater than 300 μm. For example, the thickness of the carrier 10 a is equal to or greater than 350 μm.

A package body 17 is then formed on the carrier 10 b to cover the carrier 10 a and the conductive layer 10 p. In some embodiments, the package body 17 is formed by, for example, by a transfer molding technique, a compression technique or any other suitable techniques. Since the carrier 10 b has the relatively thinner thickness (compared with the carrier 10 a), the warpage issue caused by the CTE mismatch between the carrier 10 b and the package body 17 can be mitigated even if the carrier 10 b may be in a wafer type, a panel type or a strip type. In addition, since the carrier 10 a is connected to the carrier 10 b after dividing a carrier wafer into a plurality of carriers including the carrier 10 a, the size of the divided carrier is much less than that of the carrier wafer. Hence, the warpage issue caused by the CTE mismatch between the package body 17 and the carrier 10 a can be significantly mitigated.

Referring to FIG. 5D, the carrier 59 is removed from the package body 18. A portion of the package body 18 is removed by, for example grinding or any other suitable processes to expose the interconnection structures 12 a. A circuit layer 13 including one or more conductive layers 13 c and one or more dielectric layer 13 d is formed on the package body 18 and electrically connected to the interconnection structures 12 a exposed from the package body 18. An electronic component 15 is then disposed on the circuit layer 13. In some embodiments, the active surface of the electronic component 15 is connected to the circuit layer 13 through, for example, flip-chip or any other suitable processes.

Referring to FIG. 5E, interconnection structures 12 b are formed on the circuit layer 13 and electrically connected to the circuit layer 13. In some embodiments, the interconnection structures 12 b may be formed by, for example but is not limited to, plating technique. A package body 19 is formed on the circuit layer 13 to cover the interconnection structures 12 b and the electronic component 15. In some embodiments, the package body 19 may be formed to fully cover the interconnection structures 12 b, and then a portion of the package body 19 is removed by, for example, grinding or any other suitable techniques to expose a top portion of the interconnection structures 12 b for electrical connections. In some embodiments, the package body 19 is formed by, for example, by a transfer molding technique, a compression technique or any other suitable techniques.

A circuit layer 14 including one or more conductive layers 14 c and one or more dielectric layers 14 d is formed on the package body 18 and electrically connected to the interconnection structures 12 b exposed from the package body 18. The dielectric layer 14 d is formed by, for example but is not limited to, photolithographic technique. Electrical contacts 16 are then disposed on the conductive layer 14 c exposed from the dielectric layer 14 d.

As used herein, the terms “substantially,” “substantial,” “approximately,” and “about” are used to denote and account for small variations. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a thickness of a film or a layer being “substantially uniform” can refer to a standard deviation of less than or equal to ±10% of an average thickness of the film or the layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane. Two surfaces or components can be deemed to be “substantially perpendicular” if an angle therebetween is, for example, 90°±10°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°. When used in conjunction with an event or circumstance, the terms “substantially,” “substantial,” “approximately,” and “about” can refer to instances in which the event or circumstance occurs precisely, as well as instances in which the event or circumstance occurs to a close approximation.

As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 10⁴ S/m, such as at least 10⁵ S/m or at least 10⁶ S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It can be understood that such range formats are used for convenience and brevity, and should be understood flexibly to include not only numerical values explicitly specified as limits of a range, but also all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It can be clearly understood by those skilled in the art that various changes may be made, and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus, due to variables in manufacturing processes and such. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure. 

What is claimed is:
 1. An electronic device, comprising: a circuit; a first antenna element disposed over the circuit and having a first dielectric layer and a first antenna pattern disposed on the first dielectric layer; and a second antenna element disposed over the first antenna element and having a second dielectric layer and a second antenna pattern disposed on the second dielectric layer; wherein the first antenna pattern aligns with the second antenna pattern, wherein a thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.
 2. The electronic device of claim 1, wherein the first antenna pattern is disposed between the circuit and the first dielectric layer.
 3. The electronic device of claim 2, wherein the second dielectric layer is disposed between the first dielectric layer and the second antenna pattern.
 4. The electronic device of claim 3, wherein each of the first antenna pattern and the second antenna pattern is arranged in an array.
 5. The electronic device of claim 3, further comprising a third dielectric layer encapsulating the second antenna pattern, wherein the third dielectric layer includes a material different from the second dielectric layer.
 6. The electronic device of claim 5, further comprising a fourth dielectric layer encapsulating the first antenna pattern, wherein the fourth dielectric layer includes a material different from the third dielectric layer.
 7. The electronic device of claim 6, wherein the material of the fourth dielectric layer differs from that of the first dielectric layer or the second dielectric layer.
 8. The electronic device of claim 3, further comprising an electronic component disposed over the circuit.
 9. The electronic device of claim 8, further comprising a first conductive via within the circuit and under the electronic component to connect to the first antenna pattern.
 10. The electronic device of claim 9, further comprising a second conductive via within the circuit and spaced apart from a projection of the electronic component on the circuit, wherein the second conductive via is connected to the first antenna pattern.
 11. The electronic device of claim 8, further comprising a package body covering the electronic component.
 12. The electronic device of claim 11, further comprising a third dielectric layer encapsulating the second antenna pattern, wherein the third dielectric layer includes a material substantially same as the package body.
 13. The electronic device of claim 12, wherein the third dielectric layer covers a lateral surface of the second dielectric layer.
 14. An electronic device, comprising: a circuit; a first antenna element disposed over the circuit and having a first dielectric layer and a first antenna pattern disposed on the first dielectric layer; and a second antenna element disposed over the first antenna element and having a second dielectric layer and a second antenna pattern disposed on the second dielectric layer wherein the first antenna pattern aligns with the second antenna pattern, wherein a coefficient of thermal expansion (CTE) of the first dielectric layer is greater than a CTE of the second dielectric layer.
 15. The electronic device of claim 14, wherein the first antenna pattern is disposed between the circuit and the first dielectric layer.
 16. The electronic device of claim 15, wherein the second dielectric layer is disposed between the first dielectric layer and the second antenna pattern.
 17. The electronic device of claim 16, further comprising a third dielectric layer encapsulating the second antenna pattern, wherein the third dielectric layer includes a material different from the second dielectric layer.
 18. The electronic device of claim 17, further comprising a fourth dielectric layer encapsulating the first antenna pattern, wherein the fourth dielectric layer includes a material different from the third dielectric layer.
 19. The electronic device of claim 16, wherein the first antenna pattern is arranged in an array and includes a first portion and a second portion, wherein a pitch of the first portion of the first antenna pattern is different from a distance between the first portion and the second portion of the first antenna pattern.
 20. The electronic device of claim 19, wherein the second antenna pattern is arranged in an array and includes a third portion aligned with the first portion of the first antenna pattern and a fourth portion aligned with the second portion of the second antenna pattern, wherein a pitch of the third portion of the second antenna pattern is different from a distance between the third portion and the fourth portion of the second antenna pattern. 